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IS62LV1288LL
128K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM
FEATURES
* Access times of 45, 55, and 70 ns * Low active power: 60 mW (typical) * Low standby power: 15 W (typical) CMOS standby * Low data retention voltage: 2V (min.) * Ultra Low Power * Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications * TTL compatible inputs and outputs * Single 2.5V (min.) to 3.45V (max.) power supply * Industrial temperature available * Available in 32-pin TSOP (Type I), 32-pin STSOP, and 450-mil SOP
ISSI
DESCRIPTION
(R)
FEBUARY 2001
The ISSI IS62LV1288LL is a low power and low Vcc,131,072-word by 8-bit CMOS static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62LV1288LL is available in 32-pin TSOP (Type I), STSOP (8 x 13.4mm), and 450-mil plastic SOP (525-mil pin to pin) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
512 X 2048 MEMORY ARRAY
VCC GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE1 CE2 OE WE
CONTROL CIRCUIT
This document contISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/01
1
IS62LV1288LL
PIN CONFIGURATION
32-Pin SOP (Q)
ISSI
PIN CONFIGURATION
32-Pin TSOP (Type I) (T) and STSOP (Type 1) (H)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
(R)
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
PIN DESCRIPTIONS
A0-A16 CE1 CE2 OE WE I/O0-I/O7 NC Vcc GND Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground
OPERATING RANGE
Range Commercial Ambient Temperature 0C to +70C Speed -45 ns -55 ns -70 ns -45 ns -55 ns -70 ns VCC MIN. 2.85V 2.5V 2.5V 2.85V 2.5V 2.5V VCC MAX. 3.15V 3.45V 3.45V 3.15V 3.45V 3.45V
Industrial
-40C to +85C
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/01
IS62LV1288LL
TRUTH TABLE
Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L CE1 H X L L L CE2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ISB1, ISB2 ICC ICC ICC
ISSI
(R)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM VCC TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Vcc related to GND Temperature Under Bias Storage Temperature Power Dissipation Value -0.5 to Vcc + 0.5 -0.3 to +3.6 -40 to +85 -65 to +150 0.7 Unit V V C C W
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.0V.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/01
3
IS62LV1288LL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.1 mA Min. 2.2 -- 2.0 -0.2 -1 -1 Max.
ISSI
Unit V V V V A A -- 0.4 VCC + 0.2 0.4 1 1
(R)
GND VIN VCC GND VOUT VCC
Notes: 1. VIL = -3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC ISB1 Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. -45 Min. Max. -- -- -- -- -- -- 35 40 0.4 1 8 10 -55 Min. Max. -- -- -- -- -- -- 30 35 0.4 1 8 10 -70 Min. Max. -- -- -- -- -- -- 25 30 0.4 1 8 10 Unit mA mA
VCC = Max., Com. VIN = VIH or VIL, CE1 VIH Ind. or CE2 VIL, f = 0 VCC = Max., f = 0 Com. CE1 VCC - 0.2V, Ind. CE2 0.2V, or VIN VCC - 0.2V, VIN 0.2V
ISB2
A
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/01
IS62LV1288LL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-45 Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE1 Access Time CE2 Access Time OE Access Time
(2)
ISSI
-55 Max. -- 45 -- 45 45 20 -- 15 -- -- 15 Min. 55 -- 10 -- -- -- 5 0 7 7 0 Max. -- 55 -- 55 55 25 -- 20 -- -- 20 Min. 70 -- 10 -- -- -- 5 0 10 10 0 -70 Max. -- 70 -- 70 70 35 -- 25 -- -- 25 Min. 45 -- 10 -- -- -- 0 0 5 5 0 ns ns ns ns ns ns ns ns ns ns ns
(R)
Unit
tRC tAA tOHA tACE1 tACE2 tDOE tLZOE
OE to Low-Z Output
tHZOE(2) OE to High-Z Output tLZCE1(2) CE1 to Low-Z Output tLZCE2 tHZCE
(2)
CE2 to Low-Z Output CE1 or CE2 to High-Z Output
(2)
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.3V See Figures 1 and 2
AC TEST LOADS
1213 3.0V 3.0V 1213
OUTPUT 30 pF Including jig and scope 1378
OUTPUT 5 pF Including jig and scope 1378
Figure 1.
Figure 2.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/01
5
IS62LV1288LL
AC WAVEFORMS READ CYCLE NO. 1(1,2)
ISSI
tRC
(R)
ADDRESS
tAA tOHA tOHA
DATA VALID
DOUT
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA tOHA
OE
tDOE tHZOE
CE1
tACE1/tACE2
tLZOE
CE2
tLZCE1/ tLZCE2
HIGH-Z
tHZCE
DATA VALID
DOUT
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/01
IS62LV1288LL
ISSI
-45 Min. Max. 45 35 35 35 0 0 35 25 0 -- 5 -- -- -- -- -- -- -- -- -- 15 -- -55 Min. Max. 55 50 50 50 0 0 40 25 0 -- 5 -- -- -- -- -- -- -- -- -- 20 -- -70 Min. Max. 70 60 60 60 0 0 55 30 0 0 5 -- -- -- -- -- -- -- -- -- 25 -- ns ns ns ns ns ns ns ns ns ns ns
(R)
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power)
Symbol Parameter Write Cycle Time CE1 to Write End CE2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output
(2)
Unit
tWC tSCE1 tSCE2 tAW tHA tSA tPWE1,2 tSD tHD tHZWE(2) tLZWE
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
AC WAVEFORMS WRITE CYCLE NO. 1 (CE1, CE2 Controlled, OE = HIGH or LOW)(1,2)
tWC
ADDRESS
tSCE1 tHA
CE1
tSCE2
CE2
tAW tPWE(4) tSA tHZWE
HIGH-Z
WE
tLZWE
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/01
7
IS62LV1288LL
WRITE CYCLE NO. 2 (WE, Controlled: OE is HIGH during Write Cycle)(1,2)
tWC
ISSI
(R)
ADDRESS
OE
tSCE1 tHA
CE1
tSCE2
CE2
tAW tPWE1, 2 tSA tHZWE
HIGH-Z
WE
tLZWE
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW during Write Cycle)(1,2)
tWC
ADDRESS
OE
tSCE1 tHA
CE1
tSCE2
CE2
tAW tPWE1, 2 tSA tHZWE
HIGH-Z
WE
tLZWE
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = VIH.
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/01
IS62LV1288LL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition See Data Retention Waveform Vcc = 2.0V, CE1 Vcc - 0.2V See Data Retention Waveform See Data Retention Waveform Com. Ind. Min. 2.0 -- -- 0
ISSI
Max. 3.45 8 10 -- -- Unit V A A ns ns
(R)
VDR
IDR
Vcc for Data Retention Data Retention Current Data Retention Setup Time Recovery Time
tSDR tRDR
tRC
DATA RETENTION WAVEFORM (CE1 Controlled)
tSDR VCC
Data Retention Mode
tRDR
3.0V
2.2V
VDR CE1 VCC - 0.2V
CE1 GND
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode VCC tSDR tRDR
3.0
CE2 2.2V VDR 0.4V GND
CE2 0.2V
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/01
9
IS62LV1288LL
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) Order Part No.Package 45 IS62LV1288LL-45Q IS62LV1288LL-45T IS62LV1288LL-45H IS62LV1288LL-55Q IS62LV1288LL-55T IS62LV1288LL-55H IS62LV1288LL-70Q IS62LV1288LL-70T IS62LV1288LL-70H 450-mil Plastic SOP TSOP, Type I STSOP, Type I 450-mil Plastic SOP TSOP, Type I STSOP, Type I 450-mil Plastic SOP TSOP, Type I STSOP, Type I
ISSI
(R)
55
70
Industrial Range: -40C to +85C
Speed (ns) Order Part No. 45 IS62LV1288LL-45QI IS62LV1288LL-45TI IS62LV1288LL-45HI IS62LV1288LL-55QI IS62LV1288LL-55TI IS62LV1288LL-55HI IS62LV1288LL-70QI IS62LV1288LL-70TI IS62LV1288LL-70HI Package 450-mil Plastic SOP TSOP, Type I STSOP, Type I 450-mil Plastic SOP TSOP, Type I STSOP, Type I 450-mil Plastic SOP TSOP, Type I STSOP, Type I
55
70
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/01

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